program dsPIC33EP_NMRABusNce; // ****************************************************************************** // // * Copyright: // (c) Mustangpeak Software 2012. // // The contents of this file are subject to the GNU GPL v3 licence/ you maynot use // this file except in compliance with the License. You may obtain a copy of the // License at http://www.gnu.org/licenses/gpl.html // // * Revision History: // 2012-02-01: Created // 2012-12-16 updated // // * Description: // // ***************************************************************************** uses NMRAnetNceBridge, NMRAnetStateMachine, NMRAnetDefines, NMRAnetAppCallbacks, MCU_Setup_dsPIC33EP64GP502, NMRAnetNceBridgeDefines, _25AAxxxx, NMRAnetBufferPools, NMRAnetNode, // dsPIC33_Traps, NodeIDs; {$I Options.inc} const STATE_GATHER_COMMANDSTATIONS = 0; STATE_VERIFY_COMMANDSTATIONS = 1; STATE_GATHER_PROGRAMMERS = 2; STATE_VERIFY_PROGRAMMERS = 3; STATE_INITIALIAZE = 4; STATE_RUN = 5; var // EEPROM SPI PINS CS_Bank_0 : sbit at LATB6_bit; CS_Bank_0_Direction : sbit at TRISB6_bit; EE_PROM_Hold : sbit at LATB5_bit; EEPROM_Hold_Direction : sbit at TRISB5_bit; var NceBus_RS485_Select : sbit at LATA0_bit; NceBus_RS485_Select_Direction : sbit at TRISA0_bit; // TrapFlagPin : sbit at LATB4_bit; // ***************************************************************************** // INTERRUPTS // ***************************************************************************** procedure INTERRUPT_Timer_525ms(); iv IVT_ADDR_T1INTERRUPT; begin T1IF_bit := 0; NceBusStateMachine_525ms_TimeTick; end; procedure INTERRUPT_Timer_100ms(); iv IVT_ADDR_T2INTERRUPT; // Called once every 100m var i: Integer; begin T2IF_bit := 0; // Clear the Flag for i := 0 to Nodes.AllocatedCount - 1 do NMRAnetStateMachine_100ms_Timer(Nodes.AllocatedList[i]); NMRAnetBufferPools_100ms_TimeTick; end; procedure INTERRUPT_Timer_120us(); iv IVT_ADDR_T3INTERRUPT; ics ICS_AUTO; // NceBus Timeout begin T3IF_bit := 0; end; procedure INTERRUPT_NceBus_UART_RX(); iv IVT_ADDR_U2RXINTERRUPT; begin U2RXIF_Bit := 0; // Clear the interrupt flag to receive the next byte // UART1_Write_Text('RX'); while (URXDA_U2STA_bit = 1) and (NceBusStateMachineInfo.RS485.NceBusData.StateMachineIndex < STATE_RS485_FULL) do begin NceBusStateMachine_UART_RX_StateMachine(@NceBusStateMachineInfo, U2RXREG); end end; // ******************* // MAIN LOOP // ******************* var Buffer: TCANBuffer; ActiveNode: PNMRAnetNode; i: Integer; Cmd: Char; begin SR := SR and $FF1F; // Bug in silicon? Clear the IPL bits (CPU Priority is lowest possible) _25AAxxxx_Initialize; NMRAnetStateMachine_Initialize(MUSTANGPEAK_ID_0_HI, MUSTANGPEAK_NCE_BRIDGE_NODE_ID_0_LO); MCU_Setup_Initialize; NceBusStateMachine_Initialize; UART1_Write_Text('Zeroing'+LF); AppCallback_Configuration_Zeroize(False); UART1_Write_Text('Zeroing Done'+LF); TRISB4_bit := 0; LATB4_bit := 0; // Enabled perphrials MCU_Enable_CAN; TON_T1CON_bit := 1; // Turn on TON_T2CON_bit := 1; // Turn on UART1_Write_Text('Starting'+LF); while (TRUE) do begin ActiveNode := NMRAnetNode_NextNode; if ActiveNode <> PNMRAnetNode( nil) then begin NMRAnetStateMachine_Process(ActiveNode); NceBusStateMachine_Process(@Nodes.RawList[0]); // May want this outside of Permited block, look at the statemachine end; if UART1_Data_Ready then begin Cmd := UART1_Read; case Cmd of 'a' : begin NMRAnetNode_Allocate; end; 'f' : begin UART1_Write_Text('f' + LF); NMRAnetNode_MarkForRelease(ActiveNode); end; 'Z', 'z' : begin _25AAxxxx_Erase(EEPROM_BANK_0); end; '1' : begin for i := 0 to Nodes.AllocatedCount -1 do begin IntToStr(Nodes.AllocatedList[i]^.State, s1); UART1_Write_Text('Node State: ' + s1 + LF); end; end; '2' : begin for i := ID_MIN_DEVICE to ID_MAX_DEVICE -1 do begin IntToStr(NceBusStateMachineInfo.DeviceList[i].State, s1); UART1_Write_Text('Device State: ' + s1 + LF); end; end; end end end; end.